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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532DA727
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE
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Description Features
Part number MC-4532DA727EF-A75 MC-4532DA727PF-A75 MC-4532DA727XF-A75
The MC-4532DA727 is a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 18 pieces of
128M SDRAM: PD45128441 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
* 33,554,432 words by 72 bits organization (ECC type) * Clock frequency and access time from CLK.
/CAS latency Clock frequency (MAX.) Access time from CLK (MAX.) 5.4 ns 6.0 ns 5.4 ns 6.0 ns 5.4 ns 6.0 ns 5.4 ns 6.0 ns
MC-4532DA727XFA-A75
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Programmable burst-length (1, 2, 4, 8 and Full Page) * Programmable /CAS latency (2, 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * All DQs have 10 10 % of series resistor
* Quad internal banks controlled by BA0 and BA1 (Bank Select) * Programmable wrap sequence (Sequential / Interleave)
Document No. E0073N20 (Ver.2.0) Date Published September 2001 (K) Printed in Japan
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The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
This product became EOL in September, 2002.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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CL = 3 CL = 2 133 MHz 100 MHz 133 MHz CL = 3 CL = 2 100 MHz 133 MHz CL = 3 CL = 2 100 MHz 133 MHz CL = 3 CL = 2 100 MHz
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MC-4532DA727
* Single 3.3 V 0.3 V power supply * LVTTL compatible * 4,096 refresh cycles/64 ms * Burst termination by Burst Stop command and Precharge command * 168-pin dual in-line memory module (Pin pitch = 1.27 mm) * Registered type * Serial PD
Ordering Information
Part number Clock frequency MHz (MAX.) 133 MHz 168-pin Dual In-line Memory Module 18 pieces of PD45128441G5 (Rev. E) (Socket Type) Edge connector: Gold plated 43.18 mm height (10.16mm (400) TSOP (II)) 18 pieces of PD45128441G5 (Rev. P) (10.16mm (400) TSOP (II)) 18 pieces of PD45128441G5 (Rev. X) (10.16mm (400) TSOP (II)) 30.48 mm height 18 pieces of PD45128441G5 (Rev. X) (10.16mm (400) TSOP (II)) Package Mounted devices
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MC-4532DA727EF-A75 MC-4532DA727PF-A75 MC-4532DA727XF-A75
MC-4532DA727XFA-A75
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Data Sheet E0073N20
MC-4532DA727
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated) /xxx indicates active low signal.
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 CB4 CB5 VSS NC NC Vcc /CAS DQMB4 DQMB5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 (A13) A11 Vcc CLK1 NC VSS CKE0 NC DQMB6 DQMB7 NC Vcc NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 CB0 CB1 VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 BA1(A12) Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC CB2 CB3 VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC * WP SDA SCL Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
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A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A9, A11] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0-DQ63, CB0-CB7 : Data Inputs/Outputs CLK0 - CLK3 CKE0 WP* : Clock Input : Clock Enable Input
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/CS0, /CS2 /RAS /WE /CAS DQMB0 - DQMB7 SA0 - SA2 SDA SCL VCC VSS NC : Ground REGE
Data Sheet E0073N20
: Write Protect : Chip Select Input
: Row Address Strobe : Column Address Strobe
: Write Enable
: DQ Mask Enable : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD
: Power Supply : Register / Buffer Enable
: No Connection
* : 81 pin of MC-4532DA727XFA is NC pin.
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MC-4532DA727
Block Diagram
/RCS0 RDQMB0 RDQMB4
DQ 3 DQ 2 DQ 1 DQ 0 DQ 7 DQ 6 DQ 5 DQ 4
RDQMB1
DQ 0 DQM DQ 1 D0 DQ 2 DQ 3 DQ 0 DQM DQ 1 D1 DQ 2 DQ 3
/CS
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39
RDQMB5
DQ 0 DQM /CS DQ 1 D9 DQ 2 DQ 3 DQ 0 DQM /CS DQ 1 D10 DQ 2 DQ 3
VCC C VSS D1 - D17 Register1, Register2, Register3, PLL
/CS
D1 - D17 Register1, Register2, Register3, PLL
DQ 11 DQ 10 DQ 9 DQ 8 DQ 15 DQ 14 DQ 12 DQ 13 CB 2 CB 3 CB 0 CB 1
DQ 0 DQM DQ 1 D2 DQ 2 DQ 3
/CS
DQ 40 DQ 41 DQ 42 DQ 43 DQ 45 DQ 44 DQ 46 DQ 47 CB 5 CB 4 CB 7 CB 6
DQ 0DQM /CS DQ 1 D11 DQ 2 DQ 3 DQ 0 DQM /CS DQ 1 D12 DQ 2 DQ 3 DQ 0 DQM /CS DQ 1 D13 DQ 2 DQ 3
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/RCS2 RDQMB2
DQ 0 DQM DQ 1 D3 DQ 2 DQ 3 DQ 0 DQM DQ 1 D4 DQ 2 DQ 3
/CS
SERIAL PD SCL A0 A1 A2 SDA WP
/CS
47 k
SA0 SA1 SA2
RDQMB6
MC-4532DA727XFA have no this circuit.
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DQ 0 DQM DQ 1 D5 DQ 2 DQ 3 DQ 0 DQM DQ 1 D6 DQ 2 DQ 3
/CS /CS
DQ 18 DQ 19 DQ 17 DQ 16 DQ 23 DQ 22 DQ 21 DQ 20
RDQMB3
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
DQ 0 DQM /CS DQ 1 D14 DQ 2 DQ 3 DQ 0 DQM /CS DQ 1 D15 DQ 2 DQ 3
CLK1 - CLK3
10 12 pF
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RDQMB7
DQ 27 DQ 26 DQ 25 DQ 24 DQ 31 DQ 30 DQ 29 DQ 28
10
DQ 0 DQM DQ 1 D7 DQ 2 DQ 3 DQ 0 DQM DQ 1 D8 DQ 2 DQ 3
/CS
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
DQ 0 DQM /CS DQ 1 D16 DQ 2 DQ 3
CLK0
PLL
/CS
DQ 0 DQM /CS DQ 1 D17 DQ 2 DQ 3
CLK : D0, D1, D9 CLK : D2, D10, D11 CLK : D3, D4, D12 CLK : D5, D13, D14 CLK : D6, D7, D15 CLK : D8, D16, D17 CLK : Register1, Register2,Register3
A0 - A3, A10 BA0, BA1 A4 - A9, A11 /RAS Register1 /CAS CKE0
RA0A - RA3A, RA10A RBA0A, RBA1A
A0 - A3, A10 : D0 - D3, D9 - D13 BA0, BA1
A0 - A3,A10 BA0, BA1 A4 - A9, A11
RA0B - RA3B, RA10B RBA0B, RBA1B RA4B - RA9B, RA11B /RRASB /RCASB
A0 - A3, A10 : D4 - D8, D14 - D17 BA0, BA1
RA4A - RA9A, RA11A /RRASA /RCASA RCKE0A RCKE0B
A4 - A9, A11 : D4 - D8, D14 - D17
A4 - A9, A11 : D0 - D3, D9 - D13
/RAS : D0 - D3, D9 - D13
/RAS /CAS
/RAS : D4 - D8, D14 - D17 /CAS : D4 - D8, D14 - D17
Register2
/CAS : D0 - D3, D9 - D13 CKE : D0 - D4, D9 - D12
CKE : D5 - D8, D13 - D17
/LE
REGE
/LE
DQMB0 - DQMB7
RDQMB0 - RDQMB7
VCC 10 k
/CS0, /CS2 /WE
/RCS0, /RCS2 /RWEA /RWEB
Register3
/WE : D0 - D3, D9 - D13
CKE : D4 - D8, D14 - D17
/LE
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Remarks 1. The value of all resistors of DQs is 10 . 2. D0 - D17: PD45128441 (8M words x 4 bits x 4 banks) 3. REGE VIL: Buffer mode REGE VIH: Register mode
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Data Sheet E0073N20
MC-4532DA727
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 22 0 to 70 -55 to +125 Unit V V mA W C C
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Storage temperature
Operating ambient temperature
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 TYP. 3.3 MAX. 3.6 VCC + 0.3 + 0.8 70 Unit V V V C
Supply voltage High level input voltage Low level input voltage Operating ambient temperature
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance
Data input/output capacitance
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-0.3 0 Symbol CI1 CI2 CI3 CI4 CI5 Test condition MIN. 7 TYP. A0 - A11, BA0 (A13), BA1 (A12), /RAS, /CAS, /WE CLK0 20 15 7 25 CKE0 20 /CS0, /CS2 4 10 DQMB0 - DQMB7 3 12 CI/O DQ0 - DQ63, CB0 - CB7 5 13
Data Sheet E0073N20
MAX.
Unit pF
pF
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MC-4532DA727
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current Symbol ICC1 Burst length = 1 tRC tRC (MIN.), IO = 0 mA Precharge standby current in power down mode Precharge standby current in non power down mode ICC2NS ICC3P ICC3PS ICC3N ICC2P ICC2PS ICC2N CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. CKE VIH (MIN.), tCK = , Input signals are stable. CKE VIL (MAX.), tCK = 15 ns CKE VIL (MAX.), tCK = CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC3NS ICC4 CKE VIH (MIN.), tCK = , Input signals are stable. tCK tCK (MIN.), IO = 0 mA /CAS latency = 2 /CAS latency = 3 /CAS latency = 2 /CAS latency = 3 -A75 -A75 -A75 -A75 440 2,290 2,920 4,540 4,720 286 -20 +20 mA mA 3 mA 2 224 340 152 790 mA mA Test condition /CAS latency = 2 /CAS latency = 3 Grade -A75 -A75 MIN. MAX. 2,200 2,290 268 98 610 mA mA Unit Notes mA 1
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power down mode non power down mode Operating current (Burst mode) Self refresh current Input leakage current Output leakage current Low level output voltage
Active standby current in
Active standby current in
CBR (Auto) Refresh current
High level output voltage
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
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ICC5 ICC6 II (L) IO (L) VOH VOL
tRC tRC (MIN.)
CKE 0.2 V
VI = 0 to 3.6 V, All other pins not under test = 0 V
A A
V V
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DOUT is disabled, VO = 0 to 3.6 V -1.5 2.4 +1.5 IO = -4.0 mA IO = +4.0 mA 0.4
Data Sheet E0073N20
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MC-4532DA727
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level Value 2.4 / 0.4 1.4 1 1.4 Unit V V ns V
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tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V 0.4 V tAC tOH Output tCL
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Input
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Data Sheet E0073N20
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MC-4532DA727
Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 Input clock frequency Input CLK duty cycle Data-out hold time tCK3 tCK2 tAC3 tAC2 50 45 tOH tLZ /CAS latency = 3 /CAS latency = 2 tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS 2.7 0 3.0 3.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6.0 7.5 10 -A 75 MAX. (133 MHz) (100 MHz) 5.4 6.0 133 55 ns ns ns ns MHz % ns ns ns ns ns ns ns ns ns ns ns 1 1 1 Unit Note
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Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time
Data-out low-impedance time Data-out high-impedance time
CKE setup time (Power down exit)
Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 - DQMB7) setup time
Command (/CS0, /CS2, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time
Note 1. Output load
Output
Remark These specifications are applied to the monolithic device.
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1.5 ns tCMH 0.8 ns
Z = 50 50 pF
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Data Sheet E0073N20
MC-4532DA727
Asynchronous Characteristics
Parameter Symbol MIN. ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT(one) to ACT(another) command period Data-in to PRE command period Data-in to ACT(REF) command period (Auto precharge) /CAS latency = 3 /CAS latency = 2 tRC tRC1 tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF 67.5 67.5 45 20 20 15 8 1CLK+22.5 1CLK+20 2 0.5 30 64 120,000 -A 75 MAX. ns ns ns ns ns ns ns ns ns CLK ns ms 1 Unit Note
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Transition time
Mode register set cycle time
Refresh time (4,096 refresh cycles)
Note 1. This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.
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Data Sheet E0073N20
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MC-4532DA727
Serial PD
Byte No. 0 1 2 3 4 5 6 7 8 9 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Hex 80H 08H 04H 0CH 0BH 01H 48H 00H 01H -A75 -A75 75H 54H 02H 80H 04H 04H 01H 8FH 04H 06H 01H Bit 7 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 Bit 6 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Bit 4 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Bit 3 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 Bit 2 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 1 1 0 Bit 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 Bit 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1
(1/2)
Notes 128 bytes 256 bytes SDRAM 12 rows 11 columns 1 bank 72 bits 0 LVTTL 7.5 ns 5.4 ns ECC Normal x4 x4 1 clock 1, 2, 4, 8, F 4 banks 2, 3 0 0 Registered
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10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25-26 27 28 29 30 31 tRP(MIN.) tRRD(MIN.) tRCD(MIN.) tRAS(MIN.)
Data width (continued) Voltage interface
CL = 3 Cycle time
CL = 3 Access time
DIMM configuration type Refresh rate/type
SDRAM width Error checking SDRAM width Minimum clock delay
Burst length supported
Number of banks on each SDRAM /CAS latency supported /CS latency supported
/WE latency supported
SDRAM module attributes
SDRAM device attributes : General CL = 2 Cycle time CL = 2 Access time
Module bank density
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01H 0 0 0 0 0 0 0 1 1FH 0 0 0 1 1 1 1 1 0EH 0 0 0 0 1 1 1 0 -A75 A0H 60H 1 0 1 0 0 0 0 0 -A75 0 1 1 0 0 0 0 0 00H 0 0 0 0 0 0 0 0 -A75 14H 0 0 0 1 0 1 0 0 -A75 -A75 0FH 14H 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 -A75 2DH 40H 0 0 1 0 1 1 0 1 0 1 0 0 0 0 0 0
Data Sheet E0073N20
10 ns 6 ns
20 ns
15 ns 20 ns 45 ns
256M bytes
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MC-4532DA727
(2/2)
Byte No. 32 33 34 35 36-61 62 SPD revision Function Described Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Hex 15H 08H 15H 08H 00H 02H -A75 E9H Bit 7 0 0 0 0 0 0 1 Bit 6 0 0 0 0 0 0 1 Bit 5 0 0 0 0 0 0 1 Bit 4 1 0 1 0 0 0 0 Bit 3 0 1 0 1 0 0 1 Bit 2 1 0 1 0 0 0 0 Bit 1 0 0 0 0 0 1 0 Bit 0 1 0 1 0 0 0 1 JEDEC 2 Notes 1.5 ns 0.8 ns 1.5 ns 0.8 ns
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63 64-71 72 73-90 91 93-94 95-98 99-125 126 127 Mfg specific
Checksum for bytes 0 - 62 Manufacture's JEDEC ID code
Manufacturing location Manufacture's P/N
Revision Code Manufacturing date
Assembly serial number
Intel specification frequency Intel specification /CAS latency support
Timing Chart
Refer to the PD45128441, 45128841, 45128163 Data sheet (E0031N).
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64H -A75 85H
0 1
1 0
1 0
0 0
0 0
1 1
0 0
0 1
100 MHz
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Data Sheet E0073N20
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MC-4532DA727
Package Drawing
MC-4532DA727EF, MC-4532DA727PF, MC-4532DA727XF
Front side (DATUM -A-) 3.0 min Unit: mm
4.00 max
3.00
Component area (Front)
4.00 min
4.0 0.10
17.78
Component area (Back)
R2.0
(DATUM -A-)
Detail A
2.54 0.10
1.27(T.P.)
0.20 0.15
Detail B R FULL
Detail C
(DATUM -A-)
1.00
R FULL
6.35
6.35
3.125
2.0
3.125
4.175 2.0
1.00 0.05
Note: Tolerance on all dimensions 0.15 unless otherwise specified.
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Data Sheet E0073N20
43.18 0.13
168
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1 8.89 24.495 Back side 2 - 3.00 85
84 C 36.83 42.18 133.35 0.13 B 54.61 A
11.43
1.27 0.1
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MC-4532DA727
MC-4532DA727XFA
Front side (DATUM -A-) 3.0 min Unit: mm
4.00 max
3.00
Component area (Front)
1 84 C 36.83 42.18 133.35 0.13 B 54.61 A
8.89
11.43
1.27 0.1
24.495
Back side
2 - 3.00 85
4.0 0.10
17.78
Component area (Back)
R2.0
(DATUM -A-)
Detail A
2.54 0.10
1.27(T.P.)
0.20 0.15
Detail B R FULL
Detail C
(DATUM -A-)
1.00
R FULL
6.35
6.35
3.125
2.0
3.125
4.175 2.0
1.00 0.05
Note: Tolerance on all dimensions 0.15 unless otherwise specified.
30.48 0.13
4.00 min
Data Sheet E0073N20
168
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MC-4532DA727
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0107
NOTES FOR CMOS DEVICES
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1 2 3
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
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Data Sheet E0073N20
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MC-4532DA727
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107
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